1. Field of the Invention
The present invention relates to a control method of a digital phased lock loop (DPLL) circuit and, more particularly, to a DPLL circuit used to accomplish synchronization when connecting a digital network connecting unit such as a digital service unit (DSU) with a radio unit such as a personal handy phone system (PHS).
2. Description of Related Art
FIG. 13 is a block diagram of a conventional DPLL circuit connecting a digital network connecting unit with a radio unit.
The digital network is connected to a digital network connecting unit 101; a synchronizing signal FRM output from the digital network connecting unit 101 is applied to a first input terminal of a phase comparator circuit 201 of the DPLL circuit.
A frequency dividing ratio control signal UP issued from the phase comparator circuit is supplied to a first input terminal of a first frequency divider circuit 301. The frequency dividing ratio control signal UP is a signal indicative of a phase delay. A frequency dividing ratio control signal DN issued from the phase comparator circuit is applied to a second input terminal of the first frequency divider circuit 301. The frequency dividing ratio control signal DN is a signal indicative of a phase advance. A master clock signal MCK is applied to a clock input terminal of the first frequency divider circuit 301.
An output signal CK of the first frequency divider circuit 301 is applied to the input terminal of a second frequency divider circuit 302 and the operating clock input terminal of a radio unit 401, while an output CMP of the second frequency divider circuit 302 is applied to a second input terminal of the phase comparator circuit 201.
The operation of the conventional circuit will now be described in conjunction with the timing chart shown in FIG. 14.
The circuit is set so that, if the frequency dividing ratio of the first frequency divider circuit is denoted as N and the frequency dividing ratio of the second frequency divider circuit is denoted as M, then the frequency of MCK/(Mxc3x97N)=FRM.
First, the phase of the synchronizing signal FRM issued from the digital network connecting unit is compared with the phase of the output CMP of the second frequency divider circuit 302 by the phase comparator circuit 201.
If the phase of the frequency divider circuit output CMP is later than that of the synchronizing signal FRM, then a frequency dividing ratio control signal UP is issued from the phase comparator circuit 201. The frequency dividing ratio control signal UP is output to control the frequency dividing ratio of the first frequency divider circuit to Nxe2x88x921; it is output for a preset, predetermined period of time.
Conversely, if the phase of the frequency divider circuit output CMP is earlier than that of the synchronizing signal FRM, then a frequency dividing ratio control signal DN is issued from the phase comparator circuit 201. The frequency dividing ratio control signal DN is output to control the frequency dividing ratio of the first frequency divider circuit to N+1; it is output for a preset, predetermined period of time.
For other period of time during which no control based UP or DN mentioned above is conducted, the frequency dividing ratio of the frequency divider circuit is set to N.
Thus, the DPLL circuit operates to maintain the state wherein the phase of the synchronizing signal FRM and that of the frequency divider circuit output CMP stay the same at all times. This operation permits the synchronization between the radio unit operating in accordance with the clock signal CK issued from the DPLL circuit and the digital network connecting unit issuing the synchronizing signal FRM.
When the digital network connecting unit is connected with the radio unit, the clock is turned ON/OFF at every phase comparison cycle.
The switching of the frequency dividing ratio of the DPLL circuit during transmission has been posing a problem in that the accuracy of the transmission speed is deteriorated and fails to meet a specified accuracy level.
There has been another problem in that the changeover of the frequency dividing ratio of the DPLL while a radio system is receiving data may cause a data receiving error.
The present invention has been made with a view toward solving the problems described above. A typical constitution in accordance with the present invention includes a phase control circuit for issuing a clock signal to a second device in response to a synchronizing signal supplied from a first device so as to synchronize the first device and the second device, the phase control circuit having a phase control stopping circuit that stops a phase control operation in response to a phase control disable signal issued by the second device.
According to another aspect of the present invention, there is provided a phase control method that includes a step for comparing a synchronizing signal and a signal to be controlled so as to detect a phase difference therebetween and a step for controlling the phase of the signal to be controlled in accordance with the phase difference before supplying the signal to a device, the phase control method further including a step for detecting a state wherein the device has been disabled to control the phase of the signal to be controlled, and a step for disabling the control of the phase of the signal to be controlled when the state has been engaged wherein the device has been disabled to control the phase of the signal to be controlled.